123 rad-hard msi logic UT54ACS191/ut54acts191 radiation-hardened synchronous 4-bit up-down binary counters features single down/up count control line counters fully synchronous in count modes asynchronously presetable with load control radiation-hardened cmos high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the UT54ACS191 and the ut54acts191 are synchronous 4- bit reversible up-down binary counters. synchronous counting operation is provided by having all flip-flops clocked simulta- neously so that the outputs change coincident with each other when so instructed. synchronous operation eliminates the out- put counting spikes associated with asynchronous counters. the outputs of the four flip-flops are triggered on a low-to-high- level transition of the clock input if the enable input ( cten ) is low. a logic one applied to cten inhibits counting. the di- rection of the count is determined by the level of the down/up (d/ u ) input. when d/ u is low, the counter counts up and when d/ u is high, it counts down. the counters feature a fully independent clock circuit. changes at control inputs ( cten and d/ u ) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. the counters are fully programmable. the outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. the output will change to agree with the data inputs independently of the level of the clock input. the asynchronous load allows counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs. two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (max/min) count. the max/min output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. pinouts 16-pin dip top view 16-lead flatpack top view the ripple clock output ( rco ) produces a low-level output pulse under those same conditions but only while the clock input is low. the counters easily cascade by feeding the rco to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. use the max/min count output to accomplish look-ahead for high- speed operation. the devices are characterized over full military temperature range of -55 c to +125 1 3 5 6 15 13 10 b b a d/ q q v a rco c 9 ss load 2 4 7 16 14 12 11 dd 9 q q cten u c d clk max/min c ss
rad-hard msi logic 124 UT54ACS191/ut54acts191 function table logic symbol logic diagram function load cten d/ u clk count up h l l count down h l h asynchronous reset l x x x no change h h x x (4) cten (5) d/ u m3 (up) g1 ctrdiv 16 (14) clk (15) a (1) b (10) c (9) d (12) max/min (3) q a (7) q d 1,2 -/1,3+ (6) q c (2) q b 5d (1) (2) (4) (8) 2(ct=0)z6 m2 (dwn) g4 3(ct=9)z6 (11) load c5 (13) rco 6,1,4 7 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. clk d/ u cten load (11) (9) (10) (1) (4) s r 1j c1 1k (7) (6) (2) (3) (13) (12) q d q c q b q a max/min rco a b c d (15) (5) (14) s r 1j c1 1k s r 1j c1 1k r 1j c1 1k s q q q q q q q q
125 rad-hard msi logic UT54ACS191/ut54acts191 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
rad-hard msi logic 126 UT54ACS191/ut54acts191 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
127 rad-hard msi logic UT54ACS191/ut54acts191 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
rad-hard msi logic 128 UT54ACS191/ut54acts191 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h2 ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t plh load to q n 2 20 ns t phl load to q n 2 22 ns t plh data in to q n 2 23 ns t phl data in to q n 2 19 ns t plh clk to q n 2 17 ns t phl clk to q n 2 22 ns t plh clk to rco 2 12 ns t phl clk to rco 2 15 ns t plh clk to max/min 2 22 ns t phl clk to max/min 2 23 ns t plh d/ u to rco 2 16 ns t phl d/ u to rco 2 18 ns t plh d/ u to max/min 2 15 ns t phl d/ u to max/min 2 17 ns t plh cten to rco 2 12 ns t phl cten to rco 2 16 ns f max maximum clock frequency 63 mhz t su1 load , cten , d/ u setup time before clk 12 ns t su2 a, b, c, d setup time before load 5 ns t h1 cten and d/ u hold time after clk 2 ns t h2 3 a, b, c, d hold time after load 2 ns t w minimum pulse width clk high clk low load low 8 ns
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